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| DRAM MODULE ABSOLUTE MAXIMUM RATINGS * Item Voltage on any pin relative VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC Tstg PD IOS KMM372V413CK/CS Rating -0.5 to +4.6 -0.5 to +4.6 -55 to +125 18 50 Unit V V C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70C) Item Supply Voltage Ground Input High Voltage Input Low Voltage *1 : VCC+1.3V/15ns, Pulse width is measured at VCC. *2 : -1.3V/15ns, Pulse width is measured at VSS. Symbol VCC VSS VIH VIL Min 3.0 0 2.0 -0.3*2 Typ 3.3 0 Max 3.6 0 VCC+0.3*1 0.8 Unit V V V V DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL Speed -5 -6 Dont care -5 -6 -5 -6 Dont care -5 -6 Dont care Dont care KMM372V413CK/CS Min - Max 999 909 100 999 909 819 729 30 999 909 90 9 0.4 Unit mA mA mA mA mA mA mA mA mA mA uA uA V V -90 -10 2.4 - ICC1* : Operating Current * (RAS, CAS, Address cycling @tRC=min) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3* : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) ICC4* : Fast Page Mode Current * (RAS=VIL, CAS cycling : tPC=min) ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V) ICC6* : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) II(L) : Input Leakage Current (Any input 0VINVcc+0.3V, all other pins not under test=0 V) IO(L) : Output Leakage Current(Data Out is disabled, 0VVOUTVcc) VOH : Output High Voltage Level (IOH = -2mA) VOL : Output Low Voltage Level (IOL = 2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle,tPC. DRAM MODULE CAPACITANCE (TA = 25C, Vcc=3.3V, f = 1MHz) Item Input capacitance[A0-A10, B0] Input capacitance[W0, W2, OE0, OE2] Input capacitance[RAS0 - RAS3] Input capacitance[CAS0 -1, CAS4 -5] Input/Output capacitance[DQ0 - 71] Symbol CIN1 CIN2 CIN3 CIN4 CDQ1 Min - KMM372V413CK/CS Max 15 17 45 17 24 Unit pF pF pF pF pF AC CHARACTERISTICS (0CTA70C, VCC=3.3V0.3V. See notes 1,2.) Test condition : Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V, Output loading CL=100pF Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold referenced to CAS Read command hold referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Refresh period (2K refresh) Write command set-up time CAS to W dealy time Column address to W delay time CAS precharge to W delay time Symbol Min -5 Max Min 110 155 50 18 30 5 5 2 30 50 18 48 13 18 13 10 5 8 0 10 30 0 0 -2 10 10 18 13 -2 15 32 0 36 48 53 0 40 55 60 10K 32 20 10K 18 50 5 5 3 40 60 20 58 15 18 13 10 5 8 0 10 35 0 0 -2 10 10 20 15 -2 20 32 10K 40 25 10K 20 50 60 20 35 90 133 -6 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns 7 7 7 7 9,11 9,11 11 8 8,11 11 4,11 10,11 11 11 11 11 11 3,4 3,4,5,11 3,10,11 3,11 6,11 2 Unit Note tRC tRWC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCWD tAWD tCPWD DRAM MODULE AC CHARACTERISTICS (0CTA70C, VCC=3.3V0.3V. See notes 1,2.) Test condition : Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V, Output loading CL=100pF Parameter RAS to W delay time CAS setup time(CAS-before-RAS refresh) CAS hold time(CAS-before-RAS refresh) RAS precharge to CAS hold time Access time from CAS precharge Fast page mode cycle time Fast page mode read-modify-write cycle time CAS precharge time(Fast page cycle) RAS pulse width (Fast page cycle) RAS hold time from CAS precharge W to RAS precharge time (C-B-R refresh) W to RAS hold time (C-B-R refresh) CAS precharge(C-B-R counter test) OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Present Detect Read Cycle PDE to Valid PD bit PDE to PD bit Inactive Symbol Min -5 Max Min 83 10 8 3 35 35 75 10 50 35 15 8 20 18 18 5 13 18 20 5 15 200K 40 80 10 60 40 15 8 20 71 10 8 3 KMM372V413CK/CS -6 Max Unit ns ns ns ns 40 ns ns ns ns 200K ns ns ns ns ns 20 20 ns ns ns ns Note 7,11 11 11 11 3,11 tRWD tCSR tCHR tRPC tCPA tPC tPRWC tCP tRASP tRHCP tWRP tWRH tCPT tOEA tOED tOEZ tOEH 11 11 11 11 11 11 tPD tPDOFF 10 2 7 2 10 7 ns ns DRAM MODULE NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 1TTL loads and 100pF. Voh=2.0V and Vol=0.8V. KMM372V413CK/CS 7. tWCS is not restrictive operating parameter. It included in the data sheet as electrical characteristic only. If tWCStWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the CAS leading edge in early write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If 4. Operation within the tRCD(max) limit insures that tRAC(max) tRAD is greater than the specified tRAD(max) limit, then access can be met. tRCD(max) is specified as a reference point only. time is controlled by tAA. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 11. The timing skew from the DRAM to the DIMM resulted from the addition of buffers. 5. Assumes that tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. DRAM MODULE READ CYCLE KMM372V413CK/CS tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS VIH VIL - tRCD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tOFF tAA tOEZ tOEA tCAC OE VIH VIL - DQ VOH VOL - tRAC OPEN tCLZ DATA-OUT Dont care Undefined DRAM MODULE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN KMM372V413CK/CS tRAS RAS VIH VIL - tRC tRP tCSH tCRP CAS VIH VIL - tRCD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCWL tRWL tWCS W VIH VIL - tWCH tWP OE VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined DRAM MODULE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN KMM372V413CK/CS tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS VIH VIL - tRCD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tRAD tASR tRAH tASC A VIH VIL - ROW ADDRESS tCWL tRWL W VIH VIL - tWP OE VIH VIL - tOED tDS tOEH tDH DATA-IN DQ VIH VIL - Dont care Undefined DRAM MODULE READ - MODIFY - WRTIE CYCLE KMM372V413CK/CS tRWC tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tRCD tRAD tRAH tRSH tCAS tCAH tCSH tASR VIH VIL - tASC COLUMN ADDRESS A ROW ADDR tAWD tCWD W VIH VIL - tRWL tCWL tWP OE VIH VIL - tRWD tOEA tCLZ tCAC tAA tOED tOEZ VALID DATA-OUT tDS tDH DQ VI/OH VI/OL - tRAC VALID DATA-IN Dont care Undefined DRAM MODULE FAST PAGE READ CYCLE NOTE : DOUT = OPEN KMM372V413CK/CS tRASP RAS VIH VIL o tRP tRHCP tCRP CAS VIH VIL - tPC tRCD tCAS tRAD tASC tCSH tCAH COLUMN ADDRESS tCP tCAS o tCP tRSH tCAS tASR A VIH VIL ROW ADDR tRAH tASC tCAH o o tASC tCAH COLUMN ADDRESS COLUMN ADDRESS tRRH tRCS W VIH VIL - tRCH tRCS o tRCS tRCH tCAC tOEA OE VIH VIL - tCAC tOEA o o tCAC tOEA tAA tRAC tCLZ tOEZ VALID DATA-OUT tAA tOFF tCLZ tOEZ VALID DATA-OUT tAA tOFF tCLZ VALID DATA-OUT tOFF tOEZ DQ VOH VOL - Dont care Undefined DRAM MODULE FAST PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN KMM372V413CK/CS tRASP RAS VIH VIL o tRP tRHCP tCRP CAS VIH VIL - tPC tRCD tCAS tRAD tASC tCP tCAS o tPC tCP tRSH tCAS tASR A VIH VIL - tRAH tCSH tCAH COLUMN ADDRESS tASC tCAH o o tASC tCAH ROW ADDR COLUMN ADDRESS COLUMN ADDRESS tWCS W VIH VIL - tWCH tWP tCWL tWCS tWP tWCH o tWCS tWCH tWP tCWL tRWL tCWL o o OE VIH VIL - tDS DQ VIH VIL - tDH tDS tDH o tDS tDH VALID DATA-IN VALID DATA-IN o VALID DATA-IN Dont care Undefined DRAM MODULE FAST PAGE READ - MODIFY - WRITE CYCLE KMM372V413CK/CS tRASP RAS VIH VIL - tRP tCSH tRCD tRSH tCP tCAS tRAD tRAH tASR tASC COL. ADDR tCRP tCAS tPRWC CAS VIH VIL - tCAH tRAL tASC COL. ADDR tCAH A VIH VIL - ROW ADDR tRCS W VIH VIL - tRWL tCWL tWP tCWD tAWD tRWD tOEA tOED tCAC tAA tOEZ tDH tDS tCWD tAWD tCPWD tOEA tCAC tAA tOEZ tOED tDH tDS tCWL tWP OE VIH VIL - tRAC DQ VI/OH VI/OL - tCLZ VALID DATA-OUT tCLZ VALID DATA-IN VALID DATA-OUT VALID DATA-IN Dont care Undefined DRAM MODULE RAS - ONLY REFRESH CYCLE NOTE : W, OE, DIN = Dont care DOUT = OPEN tRC KMM372V413CK/CS tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tRPC tCRP tASR A VIH VIL ROW ADDR tRAH CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Dont care tRC tRP RAS VIH VIL - tRAS tRP tRPC tCP tRPC tCSR tWRP tWRH tCHR CAS VIH VIL - W VIH VIL - tOFF DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) KMM372V413CK/CS tRC tRAS RAS VIH VIL - tRC tRP tRAS tRP tCRP CAS VIH VIL - tRCD tRSH tCHR tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWRH tRCS W VIH VIL - tRRH tWRP tAA OE VIH VIL - tOEA tCAC tRAC tCLZ tOEZ DATA-OUT tOFF DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN KMM372V413CK/CS tRC RAS VIH VIL - tRC tRP tRAS tRP tRAS tCRP CAS VIH VIL - tRCD tRAD tRSH tCHR tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWRH tWRP W VIH VIL - tWCS tWP tWCH OE VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined DRAM MODULE CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE KMM372V413CK/CS tRP RAS VIH VIL VIH VIL - tRAS tCPT tCHR tRSH tCAS tRAL tASC tCAH tCSR CAS A VIH VIL - COLUMN ADDRESS READ CYCLE W VIH VIL VIH VIL - tWRP tWRH tRCS tAA tCAC tRRH tRCH OE DQ VOH VOL - tCLZ tOEA tOEZ DATA-OUT tOFF WRITE CYCLE W VIH VIL VIH VIL - tWRP tWRH tWCS tRWL tCWL tWCH tWP OE tDS DQ VIH VIL - tDH DATA-IN READ-MODIFY-WRITE tWRP W VIH VIL - tWRH tRCS tAWD tCWD tCAC tWP tCWL tRWL tAA tOEA OE VIH VIL - tOED tCLZ tOEZ tDS tDH DQ VI/OH VI/OL VALID DATA-OUT VALID DATA-IN Dont care NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM. Undefined DRAM MODULE CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Dont care KMM372V413CK/CS tRP RAS VIH VIL - tRASS tRPS tRPC tCHS tRPC tCP CAS VIH VIL - tCSR tOFF DQ VOH VOL - OPEN tWRP tWRH W VIH VIL - TEST MODE IN CYCLE NOTE : OE, A = Dont care tRC tRP RAS VIH VIL - tRAS tRP tRPC tCP tRPC tCSR tWTS tWTH tCHR CAS VIH VIL - W VIH VIL - tOFF DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE PACKAGE DIMENSIONS KMM372V413CK/CS Units : Inches (millimeters) 5.250 (133.350) 0.118 (3.000) 5.014 (127.350) 0.054 (1.372) R 0.079 (R 2.000) 0.1570.004 (4.0000.100) 1.000 (25.40) 0.118 (3.000) .118DIA.004 (3.000DIA.100) 0.350 (8.890) 0.250 (6.350) .450 (11.430) 1.450 (36.830) 4.550 (115.57) 0.250 (6.350) 2.150 (54.61) 0.100Min (2.540Min) A B C (17.780) 0.700 ( Front view ) 0.200 Min (5.08 Min) .150Max (3.81Max) TSOP .350Max (8.89Max) SOJ ( Back view ) 0.0500.0039 (1.2700.10) 0.250 (6.350) 0.250 (6.350) (2.540 Min) 0.100 Min 0.039.002 (1.000.050) 0.123.005 (3.125.125) 0.123.005 (3.125.125) 0.01Max (0.25 Max) 0.050 (1.270) 0.079.004 (2.000.100) 0.079.004 (2.000.100) Detail A Detail B Detail C Tolerances : .005(.13) unless otherwise specified The used device is 2Mx8 DRAM with Fast Page mode, SOJ or TSOP II. (Forward) DRAM Part No. : KMM372V413CK/CS - KM48V2100CK and KM48V2100CS. Revision History Rev 0.0 : Aug. 1997 |
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